The construction of a computer system has evolved to a modular architecture, where various subsystems are implemented on daughterboards, which are connected to the motherboard. The motherboard is the main circuit board containing the primary components of the computer system. This board often contains the processor, main memory, support circuitry, and a bus controller and connector. Daughterboards, including expansion memory, input/output, and multiprocessor boards, may attach to the motherboard via a plurality of bus connectors.
Considerable effort has been made to speed up the various integrated circuits, which make up a computer system. However, as integrated circuit technologies shrink and their performance increases, the printed circuit board becomes the gating and most significant single factor limiting the speeds by which signals are transmitted on the bus lines connecting the various integrated circuits. The cycle budget for a synchronous bus can be broken into three contributing factors. One, is driving and receiving integrated circuit delays with respect to the system clock. Another is the system clock skew. The third contributor is the card net delay, which is the time required to propagate signals over the transmission lines within the network of bus lines connecting the various integrated circuits. However, improvements in the card net delay have been few.
The net delay is principally dictated by the printed circuit board ("PCB") technology, the topology of the net, and the rise and fall times of the driver circuitry. The fastest possible net is a point-to-point net. The delay of such a point-to-point net is the propagation speed of the board times the net link, plus the delay lost to a slowing of the rise and fall times due to the capacitive load introduced by the receiver. Additionally, a point-to-point solution results in the need for added buffering and additional control logic, which results in a more expensive solution. Furthermore, additional cycles are needed to implement such point-to-point nets.
Multidrop nets are more common in higher volume, lower cost systems, and are prevalent on data buses. Such nets have loads that are bidirectional. The main challenge on multidrop nets is to lay them out and route them such that the signal reflections do not significantly distort waveforms in the critical threshold regions of the receiving devices. A second challenge is arriving at a topology that optimizes all the scenarios such that delays due to reflections are minimized.
Once the integrated circuit technologies, clock distribution and mechanical requirements have been established, the card designer is left with limited possibilities in routing the net so as to not only assure that they run reliably but also optimized for speed. The normal cost of reliability of the net is additional delay.